Currently, various metal interconnections (e.g., copper interconnection structure) and their fabrication processes (e.g., electro-coppering plating (ECP)) have been developed in the semiconductor manufacturing field to electrically interconnect semiconductor devices. However, with advances of integrated circuits with ultra-large scale integration (ULSI), critical dimensions (CD) of semiconductor devices are continuously reduced and fabrication processes of metal interconnection structures are challenged.
FIGS. 1-3 show cross sectional views of a conventional copper interconnection structure at various formation stages. As shown in FIGS. 1-3, the fabrication method includes: providing a substrate 100 having a first dielectric layer 101, the first dielectric layer 101 containing an electrically conductive layer 102 and exposing a surface of the electrically conductive layer 102; forming a second dielectric layer 103 to cover both the first dielectric layer 101 and the electrically conductive layer 102; forming an opening 104 in the second dielectric layer 103 to expose the electrically conductive layer 102 (as shown in FIG. 2); forming a seed layer (not illustrated) on the sidewalls and bottom surface of the opening 104, the seed layer being made of an electrically conductive material; and filling the opening 104 completely by an ECP process to form a copper interconnection layer 105.
However, such copper interconnection structures formed by conventional techniques provide undesired performance and it is desirable to provide stable electrical interconnections with high quality electrical isolations.